Travel Grant report
by
Radoslaw Szymanek
(June-2003)

Design Automation Conference is the biggest and the most prestigious event in Electronic Design Automation Community. This year more then 5000 participants came to Anaheim and I was one of them. I came to Anaheim few days earlier so it was easier for me to adapt to a different time zone. The conference consisted of many parallel events. I myself spend all three days from the morning until late evening at the conference site. Conference attracts probably more people from industry than academia.

The conference was opened Tuesday morning by program and executive committee of DAC. It was shortly followed by very interesting keynote speech by Sir Robin Saxby, who is CEO of ARM. His speech was titled "100nm ... a giant leap for mankind?". Very interesting talk about possible future which will be heavily influenced by current developments in Electronic Design Automation industry. Tuesday morning I partially followed panel discussion about reshaping EDA industry for power. Later, I went to see one article presentation in session about Embedded Hardware Design Studies. Right after this session during lunch break I went for the first time to the exhibit floor. There were more then 200 companies presenting themselves and their work. Just a walk through the whole exhibition forum plus few short conversations ate away my two hours lunch break. After lunch break I went back to the presentation floor to the next embedded system session. This session was about Lower-Power Embedded System Design.

I left a bit earlier this time since next session will be my session and I wanted to do last minute preparation and relax a bit. At 16.30 I was introduced by Nikil Dutt, who was the chairman of my session. My talk was scheduled to take maximum 25 minutes followed by 5 minutes question time. I talked about constraints driven synthesis and partial assignment technique to simply partitioning and scheduling problem. My work touches on problems which are not easy to solve and even 25 minutes is not enough to give deep overview of my method. Hopefully people working with this type of problems were able to grasp some intuition behind my approach. After my presentation I have received one question from the chairman and four questions from the audience. The questions I have received indicated that some people did manage to get a good overview of my method and if necessary could deepen it by reading my article. In my session there was a presentation of the paper from Swiss Federal Institute of Technology by Kubilay Atasu and et. This paper was later given the best paper award. After my session I could relax, I went to a PhD forum where I could see what other students are doing.

Wednesday morning I have spent discussing with people from companies such as Celoxica, Magma, Cadence, Synopsis, Mentor Graphics. I have followed more then 5 different presentations of the recent developments in those companies. After lunch I have followed very interesting session about Novel Techniques in High Level Synthesis. After this session I decided to go to another panel discussion which had a following title "Nanometer Design: Place Your Bets". Each of the panelists had a very interesting view about the future developments and what he thinks will have highest impact on industry. I particularly liked the insights of John Cohn from IBM. All panelist have agreed that the biggest challenges ahead lies at technology level, when it comes to producing chips that more and more variability of all processes comes to the picture which make it more and more difficult to produce correct chip. After this panel I spend evening hours talking to few other companies like Intel, Accel Chip, and Synplicity. Very interesting long discussion I had with people from Accel Chip, who are starting their embedded system design flow in MATLAB, which raises the modeling level quite high.

Last day of the conference I spent in two panels and two sessions. First panel was about the importance of the libraries and modular design flow, where the second was about significance of formal verification methods and simulation in debugging and verification process of the electronic circuits. Both panels had a vivid and hot discussion with high degree of interaction with the audience. The main message of the first panel was that libraries help to decrease time to market. The important message of the second panel was that verification takes nowadays at least 50% of project time and gets longer and longer and there are immediate needs to short that. Formal verification can help in achieving faster verification, but will never replace simulation.

In the middle of the day there was a keynote speech by professor Alberto L. Sangiovanni-Vicentelli from university of California, Berkeley, CA. This speech compared the phases of the EDA industry to a Greek mythology where there was an age of gods, heros, and people. Great speech with amazing overview of the most significant developments in EDA and interesting insights to the future. One of most interesting statements from my point of view was that the process designing of chips has to go to higher levels of abstractions in order to cope with chip complexities.

I had a great time at the conference. I only wish there were not so many parallel sessions, panels which forced me to miss some other interesting discussions or presentations. I had a chance to meet many important people in our field, see for myself what is the state of the art in my field, and participate in discussion about current and future work in our field.